# |
Patent # |
Title |
|
1 |
10179078 |
Therapeutic method and device for
rehabilitation |
|
2 |
10177648 |
Circuit with low DC bias storage
capacitors for high density power conversion |
|
3 |
9893604 |
Circuit with low DC bias storage
capacitors for high density power conversion |
|
4 |
9889058 |
Orthotic device drive system and method |
|
5 |
9474673 |
Methods and devices for deep vein
thrombosis prevention
|
|
6 |
9131873 |
Foot pad device and method of obtaining
weight data |
|
7 |
8679040 |
Intention-based therapy device and
method |
|
8 |
8639455 |
Foot pad device and method of obtaining
weight data |
|
9 |
8353854 |
Method and devices for moving a body
joint |
|
10 |
8274244 |
Actuator system and method for
extending a joint
|
|
11 |
8058823 |
Actuator system with a multi-motor
assembly for extending and flexing a joint |
|
12 |
7811189 |
Deflector assembly |
|
13 |
7648436 |
Rotary actuator |
|
14 |
7537573 |
Active muscle assistance and resistance
device and method
|
|
15 |
7521836 |
Electrostatic actuator with fault
tolerant electrode structure
|
|
16 |
7484038 |
Method and apparatus to manage storage
devices |
|
17 |
7468982 |
Method and apparatus for cluster
interconnection using multi-port nodes and multiple routing fabrics |
|
18 |
7365463 |
High-torque motor |
|
19 |
7239065 |
Electrostatic actuator with fault
tolerant electrode structure
|
|
20 |
6966882 |
Active muscle assistance device and
method |
|
21 |
6950428 |
System and method for configuring
adaptive sets of links between routers in a system area network (SAN) |
|
22 |
6924780 |
Spatial display of disk drive activity
data |
|
23 |
6775794 |
Use of activity bins to increase the
performance of disk arrays
|
|
24 |
6753878 |
Parallel pipelined merge engines |
|
25 |
6751757 |
Disk drive data protection using
clusters containing error detection sectors |
|
26 |
6650533 |
Pluggable drive carrier assembly |
|
27 |
6646984 |
Network topology with asymmetric
fabrics |
|
28 |
6631131 |
Transpose table biased arbitration
scheme |
|
29 |
6591339 |
Methods and systems for selecting block
sizes for use with disk arrays
|
|
30 |
6591338 |
Methods and systems for mirrored disk
arrays |
|
31 |
6567892 |
Use of activity bins to increase the
performance of disk arrays
|
|
32 |
6549977 |
Use of deferred write completion
interrupts to increase the performance of disk operations |
|
33 |
6516032 |
First-order difference compression for
interleaved image data in a high-speed image compositor |
|
34 |
6496940 |
Multiple processor system with standby
sparing |
|
35 |
6487633 |
Methods and systems for accessing disks
using forward and reverse seeks
|
|
36 |
6484235 |
Methods and systems for dynamically
distributing disk array data accesses |
|
37 |
6424655 |
Transpose table-biased arbitration |
|
38 |
6424523 |
Pluggable drive carrier assembly |
|
39 |
6266765 |
Computer architecture capable of
execution of general purpose multiple instructions |
|
40 |
6233702 |
Self-checked, lock step processor pairs |
|
41 |
6157967 |
Method of data communication flow
control in a data processing system using busy/ready commands |
|
42 |
6092177 |
Computer architecture capable of
execution of general purpose multiple instructions |
|
43 |
6009506 |
Computer architecture capable of
concurrent issuance and execution of general purpose multiple instructions |
|
44 |
5964835 |
Storage access validation to data
messages using partial storage address data indexed entries containing
permissible address range validation for message source |
|
45 |
5930275 |
Clock error detection circuit |
|
46 |
5918032 |
Computer architecture capable of
concurrent issuance and execution of general purpose multiple instructions |
|
47 |
5914953 |
Network message routing using routing
table information and supplemental enable information for deadlock prevention |
|
48 |
5890003 |
Interrupts between asynchronously
operating CPUs in fault tolerant computer system |
|
49 |
5867501 |
Encoding for communicating data and
commands |
|
50 |
5838894 |
Logical, fail-functional, dual central
processor units formed from three processor units |
51 |
5765007 |
Microinstruction sequencer having
multiple control stores for loading different rank registers in parallel |
|
52 |
5758113 |
Refresh control for dynamic memory in
multiple processor system
|
|
53 |
5752064 |
Computer architecture capable of concurrent
issuance and execution of general purpose multiple instructions |
|
54 |
5751932 |
Fail-fast, fail-functional,
fault-tolerant multiprocessor system
|
|
55 |
5742135 |
System for maintaining polarity
synchronization during AMI data transfer |
|
56 |
5710549 |
Routing arbitration for shared
resources |
|
57 |
5694121 |
Latency reduction and routing
arbitration for network message routers |
|
58 |
5675579 |
Method for verifying responses to
messages using a barrier message
|
|
59 |
5628024 |
Computer architecture capable of
concurrent issuance and execution of general purpose multiple instructions |
|
60 |
5574941 |
Computer architecture capable of
concurrent issuance and execution of general purpose multiple instruction |
|
61 |
5574933 |
Task flow computer architecture |
|
62 |
5404550 |
Method and apparatus for executing
tasks by following a linked list of memory packets |
|
63 |
5390355 |
Computer architecture capable of
concurrent issuance and execution of general purpose multiple instructions |
|
64 |
5384906 |
Method and apparatus for synchronizing
a plurality of processors
|
|
65 |
5353436 |
Method and apparatus for synchronizing
a plurality of processors
|
|
66 |
5329629 |
Apparatus and method for reading,
writing, and refreshing memory with direct virtual or physical access |
|
67 |
5317726 |
Multiple-processor computer system with
asynchronous execution of identical code streams |
|
68 |
5287472 |
Memory system using linear array wafer
scale integration architecture
|
|
69 |
5239641 |
Method and apparatus for synchronizing
a plurality of processors
|
|
70 |
5203005 |
Cell structure for linear array wafer
scale integration architecture with capability to open boundary I/O bus
without neighbor acknowledgement
|
|
71 |
5193175 |
Fault-tolerant computer with three
independently clocked processors asynchronously executing identical code that
are synchronized upon each voted access to two memory modules |
|
72 |
5146589 |
Refresh control for dynamic memory in
multiple processor system
|
|
73 |
5075844 |
Paired instruction processor precise
exception handling mechanism
|
|
74 |
5072364 |
Method and apparatus for recovering
from an incorrect branch prediction in a processor that executes a family of
instructions in parallel
|
|
75 |
5034964 |
N:1 time-voltage matrix encoded I/O
transmission system
|
|
76 |
5016208 |
Deferred comparison multiplier checker |
|
77 |
4872109 |
Enhanced CPU return address stack |
|
78 |
4823252 |
Overlapped control store |
|
79 |
4800486 |
Multiple data patch CPU architecture |
|
80 |
4754396 |
Overlapped control store |
|
81 |
4636943 |
Enhanced CPU microbranching
architecture |
|
82 |
4618956 |
Method of operating enhanced alu test
hardware |
|
83 |
4574344 |
Entry control store for enhanced CPU
pipeline performance
|
|
84 |
4571673 |
Enhanced CPU microbranching
architecture |