Robert W. Horst, Ph. D. - Horst Technology Consulting

Patents

#	Patent #	Title	PDF
1	10179078	Therapeutic method and device for rehabilitation The invention relates to embodiments of methods for extending a subject-controllable range of joint motion, and for increasing subject control of joint movement within a range of motion....
2	10177648	Circuit with low DC bias storage capacitors for high density power conversion A circuit for converting DC to AC power or AC to DC power comprises a storage capacitor, boost and buck inductors and switching elements. The switches are controlled to steer current to and from...
3	9893604	Circuit with low DC bias storage capacitors for high density power conversion A circuit for converting DC to AC power or AC to DC power comprises a storage capacitor, boost and buck inductors and switching elements. The switches are controlled to steer current to and from...
4	9889058	Orthotic device drive system and method An orthosis includes a first portion and a second portion configured to attach on opposite sides of a joint. An actuator is configured to apply a force between the first and second portions. The...
5	9474673	Methods and devices for deep vein thrombosis prevention Portable devices and methods for preventing deep vein thrombosis (DVT) by assuring that the ankle is flexed and extended sufficiently to promote blood flow in the lower leg are disclosed. The...
6	9131873	Foot pad device and method of obtaining weight data A foot pad device includes a foot pad, force sensors that provide force data, sensor electronics coupled to the force sensors, and a processor. The foot pad includes a ball region configured to be...
7	8679040	Intention-based therapy device and method A method for controlling movement using an active powered device including an actuator, joint position sensor, muscle stress sensor, and control system. The device provides primarily muscle...
8	8639455	Foot pad device and method of obtaining weight data A foot pad device and a method of obtaining weight data from a force sensor in a foot pad worn by a user engaging in a footstep, including placing the force sensor under the ball of the foot of...
9	8353854	Method and devices for moving a body joint Portable devices and methods for preventing deep vein thrombosis (DVT) by assuring that the ankle is flexed and extended sufficiently to promote blood flow in the lower leg are disclosed. The...
10	8274244	Actuator system and method for extending a joint An actuator system for assisting extension of a biological joint is provided with a motor assembly, a rotary-to-linear mechanism, and an extension stop. The rotary-to-linear mechanism includes a...
11	8058823	Actuator system with a multi-motor assembly for extending and flexing a joint An actuator system for extending and flexing a joint, including a multi-motor assembly for providing a rotational output, a rotary-to-linear mechanism for converting the rotational output from the...
12	7811189	Deflector assembly A technique for deflecting an actuator belt includes applying a variable deflection force to the actuator belt. The technique may be used to construct actuators for active orthotics, robotics or...
13	7648436	Rotary actuator A technique for providing a variable-ratio coupling between output shaft and input motor involves driving an output shaft with drivers that are out of phase with each other. Advantageously, the...
14	7537573	Active muscle assistance and resistance device and method A method for controlling movement using an active powered device including an actuator, joint position sensor, muscle stress sensor, and control system. The device provides primarily muscle...
15	7521836	Electrostatic actuator with fault tolerant electrode structure A high-power electrostatic actuator comprising rotor and stator layers with fault-tolerant electrode structures, a housing to contain the electrodes and dielectric fluid, and electronic circuitry...
16	7484038	Method and apparatus to manage storage devices A method and apparatus to manage storage devices has been disclosed. In one embodiment, the method includes logically partitioning each of a number of storage devices in a networked data storage...
17	7468982	Method and apparatus for cluster interconnection using multi-port nodes and multiple routing fabrics Interconnect networks are described that allow nodes having more than two ports to be interconnected. More particularly, each node interfaces with multiple and more than two, fabrics. Also, all...
18	7365463	High-torque motor A motor that delivers high force linear motion or high torque rotary motion to a moving element. The motor may include a driving brake, a driver, a holding brake and a flexible moving element....
19	7239065	Electrostatic actuator with fault tolerant electrode structure A high-power electrostatic actuator comprising rotor and stator layers with fault-tolerant electrode structures, a housing to contain the electrodes and dielectric fluid, and electronic circuitry...
20	6966882	Active muscle assistance device and method A method for controlling movement using an active powered device including an actuator, joint position sensor, muscle stress sensor, and control system. The device provides primarily muscle...
21	6950428	System and method for configuring adaptive sets of links between routers in a system area network (SAN) Adaptive sets of lanes are configured between routers in a system area network. Source nodes determine whether packets may be adaptively routed between the lanes by encoding adaptive control bits...
22	6924780	Spatial display of disk drive activity data Real time disk activity data for a disk drive is displayed on a multi-element display in which each display element corresponds to a respective address range or “activity bin” of the disk drive....
23	6775794	Use of activity bins to increase the performance of disk arrays A disk array controller reliably improves performance in RAID configurations without the need for a battery backup. Write completion interrupts are queued until a write cache flush has been...
24	6753878	Parallel pipelined merge engines An image generator is organized into a plurality of rendering engines, each of which renders an image of a part scene and provides the part image to a merge engine associated with that rendering...
25	6751757	Disk drive data protection using clusters containing error detection sectors The present invention is related to methods and apparatus that can enhance the reliability of a hard drive by providing a built-in error check in the drive. Conventional hard drives can...
26	6650533	Pluggable drive carrier assembly A computer system with a pluggable drive carrier assembly comprises a cabinet and a circuit board disposed within the cabinet. The circuit board, such as a base board, has a number of connectors...
27	6646984	Network topology with asymmetric fabrics Enhanced performance is realized in a multi-fabric/multi switch group interconnect network by providing asymmetric fabric topologies wherein at least one link between a user-port and a switch-port...
28	6631131	Transpose table biased arbitration scheme A biased arbitration technique utilizes a transpose table to arbitrate access to a shared resource. Each column of transpose table is a binary bias vector encoding a bias value assigned to one of...
29	6591339	Methods and systems for selecting block sizes for use with disk arrays The present invention is related to methods and systems for improving the read performance of a drive array, such as a RAID 5 array, having an “n” number of drives so that the read performance is...
30	6591338	Methods and systems for mirrored disk arrays The present invention is related to methods and systems for providing different stripe sizes for different zones for at least a first of a plurality of mirrored drives to improve data rates. The...
31	6567892	Use of activity bins to increase the performance of disk arrays A disk array controller reliably improves performance in RAID configurations without the need for a battery backup. Write completion interrupts are queued until a write cache flush has been...
32	6549977	Use of deferred write completion interrupts to increase the performance of disk operations A disk array controller reliably improves performance in RAID configurations without the need for a battery backup. Write completion interrupts are queued until a write cache flush has been...
33	6516032	First-order difference compression for interleaved image data in a high-speed image compositor An encoder accepts an N byte set of values for each of a plurality of image components, with N being greater than one and, for each N byte set of values, identifies a compressed symbol length, K,...
34	6496940	Multiple processor system with standby sparing A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device,...
35	6487633	Methods and systems for accessing disks using forward and reverse seeks The present invention is related to methods and systems for accessing multimedia data stored on a disk array to ensure that the transfer rate does not fall below a selected minimum transfer rate...
36	6484235	Methods and systems for dynamically distributing disk array data accesses The present invention is related to methods and systems for reducing head movements during accesses to drives within a drive array by dynamically selecting which one of a first drive and a second...
37	6424655	Transpose table-biased arbitration A biased arbitration technique utilizes a transpose table to arbitrate access to a shared resource. Each column of transpose table is a binary bias vector encoding a bias value assigned to one of...
38	6424523	Pluggable drive carrier assembly A computer system with a pluggable drive carrier assembly comprises a cabinet and a circuit board disposed within the cabinet. The circuit board, such as a base board, has a number of connectors...
39	6266765	Computer architecture capable of execution of general purpose multiple instructions A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether...
40	6233702	Self-checked, lock step processor pairs A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device,...
41	6157967	Method of data communication flow control in a data processing system using busy/ready commands A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device,...
42	6092177	Computer architecture capable of execution of general purpose multiple instructions A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether...
43	6009506	Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether...
44	5964835	Storage access validation to data messages using partial storage address data indexed entries containing permissible address range validation for message source A multiprocessor system includes a number of central processing unit (CPUs) and at least one input/output (I/O) device interconnected by routing apparatus for communicating packetized messages...
45	5930275	Clock error detection circuit A method and digital circuit for indicating whether the frequencies of two clocks are within a predetermined range of each other, wherein a first pattern of alternating binary one's and zero's is...
46	5918032	Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether...
47	5914953	Network message routing using routing table information and supplemental enable information for deadlock prevention A processing system includes multiple processor units and multiple input/output elements communicatively interconnected by a system area network having a plurality of multi-ported router elements....
48	5890003	Interrupts between asynchronously operating CPUs in fault tolerant computer system A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the...
49	5867501	Encoding for communicating data and commands A method of encoding data and commands as N-bit words includes using a first portion of the word to identify whether the word carries data or a command. In the case of a command, the command is in...
50	5838894	Logical, fail-functional, dual central processor units formed from three processor units A computing system includes a pair of central processor units structured to operate in substantial synchronism to each execute the same instruction at substantially the same moment in time of...

51	5765007	Microinstruction sequencer having multiple control stores for loading different rank registers in parallel First and second banks of control stores are used to store microinstructions. Each bank contains three control stores: A horizontal control store, a vertical control store, and a jump control...
52	5758113	Refresh control for dynamic memory in multiple processor system A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the...
53	5752064	Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether...
54	5751932	Fail-fast, fail-functional, fault-tolerant multiprocessor system A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device,...
55	5742135	System for maintaining polarity synchronization during AMI data transfer A communication system transmitting AMI encoded data forces a latent error to occur within a predetermined time duration from an event which generated the latent error. Bit values of original data...
56	5710549	Routing arbitration for shared resources A data communicating device, having a number of inputs whereat data is received for communication from one of a number of outputs of the device, includes apparatus for providing two levels of...
57	5694121	Latency reduction and routing arbitration for network message routers A data communicating device, having a number of inputs whereat data is received for communication from one of a number of outputs of the device, includes apparatus for selecting one of the inputs...
58	5675579	Method for verifying responses to messages using a barrier message A processing system includes a number of communicatively interconnected system elements structured to send and receive data in the form of message packets. Message packets sent to a destination...
59	5628024	Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether...
60	5574941	Computer architecture capable of concurrent issuance and execution of general purpose multiple instruction A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether...
61	5574933	Task flow computer architecture A computer architecture has a plurality of processing cells interconnected to perform programming tasks. Each cell contains both memory and processing elements. Memory packets contain an...
62	5404550	Method and apparatus for executing tasks by following a linked list of memory packets A computer architecture has a plurality of processing cells interconnected to perform programming tasks. Each cell contains both memory and processing elements. Memory packets contain an...
63	5390355	Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether...
64	5384906	Method and apparatus for synchronizing a plurality of processors A method and apparatus for synchronizing a plurality of processors. Each processor runs off its own independent clock, indicates the occurrence of a prescribed process or event on one line and...
65	5353436	Method and apparatus for synchronizing a plurality of processors A method and apparatus for synchronizing a plurality of processors. Each processor runs off of its own independent clock, indicates the occurrence of a prescribed process or event on one line and...
66	5329629	Apparatus and method for reading, writing, and refreshing memory with direct virtual or physical access A computer memory system is provided. Received memory requests can be for addresses which are virtual or physical. The type of address is determined, and a virtual/physical bit is set and stored....
67	5317726	Multiple-processor computer system with asynchronous execution of identical code streams A fault-tolerant computer system employs multiple identical CPUs executing the same instruction stream, each with their own independent memory. The multiple CPUs are loosely synchronized, as by...
68	5287472	Memory system using linear array wafer scale integration architecture A cell architecture for use in a linear array wafer scale integration includes a plurality of multiplexers, each associated with a boundary of the cell, and each selectively operable to permit...
69	5239641	Method and apparatus for synchronizing a plurality of processors A method and apparatus for synchronizing a plurality of processors. Each processor runs off of its own independent clock, indicates the occurrence of a prescribed process or event on one line and...
70	5203005	Cell structure for linear array wafer scale integration architecture with capability to open boundary I/O bus without neighbor acknowledgement A cell architecture for use in a linear array wafer scale integration includes a plurality of multiplexers, each associated with a boundary of the cell, and each selectively operable to permit...
71	5193175	Fault-tolerant computer with three independently clocked processors asynchronously executing identical code that are synchronized upon each voted access to two memory modules A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the...
72	5146589	Refresh control for dynamic memory in multiple processor system A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the...
73	5075844	Paired instruction processor precise exception handling mechanism A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for...
74	5072364	Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel A branch recovery mechanism completes the processing of a concurrently issued family of instructions depending on the location of the branch instruction in the family and on whether the branch was...
75	5034964	N:1 time-voltage matrix encoded I/O transmission system Encoding and decoding circuits are described for functioning as both a time and voltage based transmission system. Multiple binary inputs can be transmitted and received on a single I/O pin by...
76	5016208	Deferred comparison multiplier checker In a data processing system, a multiplication operation is immediately followed by a redundant multiplication operation, using the same, albeit altered, operands, to check the initial result. The...
77	4872109	Enhanced CPU return address stack Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit...
78	4823252	Overlapped control store An interleaved control store having a soft error recovery system. The system includes memory banks storing identical data sets, an error detection unit for indicating that an erroneous data...
79	4800486	Multiple data patch CPU architecture The various functional units which comprise a central processing unit of a computer are organized so as to enable a main arithmetic logic unit and special function units including an auxilliary...
80	4754396	Overlapped control store An overlapped control store including a pair of memory elements, with each element in the pair storing a complete instruction set and with instructions from the elements accessed on alternate...
81	4636943	Enhanced CPU microbranching architecture Hardware for performing microcode branching in a central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally inhibit...
82	4618956	Method of operating enhanced alu test hardware Method and hardware associated with an arithmetic logic unit (ALU) in a central processing unit of a data processor provides for testing the inputs to the ALU to see if logical AND is zero or the...
83	4574344	Entry control store for enhanced CPU pipeline performance An entry control store in a central processing unit (CPU) is addressed by the next macroinstruction to be executed by the CPU and fetches the microcode for the first line of that macroinstruction....
84	4571673	Enhanced CPU microbranching architecture Hardware for performing microcode branching in a pipeline central processing unit allows for two different speeds of branches which can be used by microcode and includes flexibility to optionally...

Computer design and architecture

Fault tolerant computing

CPU, cache and memory design

I/O and storage subsystems

High speed networks

Performance evaluation

Hardware testing

Patents and intellectual property

Robotics and motor control

Power electronics

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